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CY7C133 CY7C143
2K x 16 Dual-Port Static RAM
Features
* True dual-ported memory cells which allow simultaneous reads of the same memory location * 2K x 16 organization * 0.65-micron CMOS for optimum speed/power * High-speed access: 25/35/55 ns * Low operating power: ICC = 150 mA (typ.) * Fully asynchronous operation * Master CY7C133 expands data bus width to 32 bits or more using slave CY7C143 * BUSY input flag on CY7C133; BUSY output flag on CY7C143 * Available in 68-pin PLCC * Pin-compatible and functionally equivalent to IDT7133 and IDT7143
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C143 slave dual-port device in systems requiring 32-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; Chip Enable (CE), Write Enable (R/WUB, R/WLB), and Output Enable (OE). BUSY signals that the port is trying to access the same location currently being accessed by the other port. An automatic power-down feature is controlled independently on each port by the Chip Enable (CE) pin. The CY7C133 and CY7C143 are available in 68-pin PLCC.
Logic Block Diagram
CEL R/WLUB CER R/WRUB
R/WLLB OEL
R/WRLB OER
I/O8L - I/O15L I/O0L - I/O7L BUSYL[1] A10L A0L ADDRESS DECODER
I/O CONTROL
I/O CONTROL
I/O8R - I/O15R I/O0R - I/O7R BUSYR
[1]
MEMORY ARRAY
ADDRESS DECODER
A10R A0R
CE L OE L R/WLUB R/WLLB
ARBITRA TION LOGIC (CY7C133 ONLY)
CER OER R/WRUB R/WRLB C133-1
Note: 1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 14, 1999
CY7C133 CY7C143
Pin Configuration
68-Pin LCC/PLCC Top View
I/O3L I/O2L I/O1L I/O0L V CC R/WLUB R/WLLB OEL I/O8L I/O7L I/O6L I/O5L I/O4L A10L A9L A8L A7L 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 I/O8R I/O9R I/O 10R I/O 11R I/O 12R I/O 13R I/O 14R I/O 15R GND R/W RUB R/W RLB OER A 10R A9R A 8R A7R A6R A6L A5L A4L A3L A2L A1L A0L BUSYL CEL CER BUSYR A0R A1R A2R A3R A4R A5R
9876 I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
5 4 3 2 1 68 67 66 65 64 63 62 61
7C133 7C143
C133-2
Selection Guide
7C133-25 7C143-25 Maximum Access Time (ns) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) 25 170 40 7C133-35 7C143-35 35 160 30 7C133-55 7C143-55 55 150 20
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V
DC Input Voltage ................................................. -3.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
2
CY7C133 CY7C143
Electrical Characteristics Over the Operating Range
7C133-25 7C143-25 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[3,4] GND < VI < VCC GND < VO < V CC, Output Disabled VCC = Max., VOUT = GND Com'l Ind. Com'l Ind. 170 170 40 40 100 100 3 3 90 90 -5 -5 VCC = Min., IOH = -4.0 mA IOL = 4.0 mA IOL = 16.0 mA
[2]
Test Conditions
Min. 2.4
Typ.
Max.
Unit V
0.4 0.5 2.2 0.8 +5 +5 -200 250 290 60 75 140 160 15 15 120 140
V V V A A mA mA
VCC Operating Supply Cur- CE = VIL, rent Outputs Open, f = fMAX[5] Standby Current Both Ports, CEL and CER > VIH, f = fMAX[5] TTL Inputs
ISB1 ISB2 ISB3
mA mA mA
Standby Current One Port, CEL or CER > VIH, Active Port Out- Com'l TTL Inputs puts Open, f = fMAX[5] Ind. Standby Current Both Ports, Both Ports CEL and CER > VCC - Com'l CMOS Inputs 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Ind. f=0 Standby Current One Port, One Port CEL or CER > VCC - 0.2V, Com'l CMOS Inputs VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, Ind. f = fMAX[5]
ISB4
mA
Notes: 2. BUSY pin only. 3. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. 5. At f=f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
3
CY7C133 CY7C143
Electrical Characteristics Over the Operating Range (continued)
7C133-35 7C143-35 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage GND < VO < VCC, Output Disabled Current Output Short Circuit Current[3,4] VCC = Max., VOUT = GND Com'l Ind. 160 160 30 30 85 85 3 3 80 80 -5 -5 Test Conditions VCC = Min., IOH = -4.0 mA IOL = 4.0 mA IOL = 16.0 mA
[2]
7C133-55 7C143-55 Min. 2.4 0.4 0.5 0.4 0.5 2.2 0.8 +5 +5 -5 -5 0.8 +5 -5 -200 150 150 20 20 75 75 3 3 70 70 220 250 40 55 110 125 15 15 90 105 mA mA mA mA V V A A mA mA Typ. Max. Unit V V
Min. 2.4
Typ.
Max.
2.2
-200 230 260 50 65 125 140 15 15 105 120
VCC Operating Supply CE = VIL, Current Outputs Open, f = fMAX[5] Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs Standby Current One Port, CMOS Inputs
ISB1 ISB2 ISB3
CEL and CER > VIH, f = fMAX[5] Com'l Ind. CEL or CER > V IH, Active Port Com'l Outputs Open, f = fMAX[5] Ind. Both Ports CEL and CER > Com'l VCC - 0.2V, VIN > VCC - 0.2V Ind. or VIN < 0.2V, f = 0 One Port CEL or CER > VCC - Com'l 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Ind. Open, f = fMAX[5]
ISB4
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 347 R1893 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 347 BUSY OR INT R1893 5V 281
30 pF (b) 3.0V GND < 3 ns 10%
C133-3
(a)
C133-2
ALL INPUT PULSES Equivalent to: THEVENIN EQUIVALENT 250 OUTPUT 1.40V 90% 90% 10% < 3 ns
BUSY Output Load (CY7C133ONLY)
C133-4
4
CY7C133 CY7C143
Switching Characteristics Over the Operating Range[6]
7C133-25 7C143-25 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid[7] Data Hold from Address Change CE LOW to Data Valid
[7] [7]
7C133-35 7C143-35 Min. 35 Max.
7C133-55 7C143-55 Min. 55 Max. Unit ns 55 0 55 30 3 25 5 20 0 25 55 40 40 2 0 35 20 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 0 ns ns
Description
Min. 25
Max.
25 0 25 20 3 15 3 15 0
[10]
35 0 35 25 3 20 5 20 0 25 35 25 25 2 0 25 20 0
OE LOW to Data Valid OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
OE LOW to Low Z[8, 9,10]
[8, 9,10] [8, 9,10] [8, 9,10]
CE LOW to Power-Up[10] CE HIGH to Power-Down
[11]
25 25 20 20 2 0 20 15 0 15 0 0
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z [9,10] R/W HIGH to Low Z
[9,10]
20
Notes: 6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 7. AC Test Conditions use VOH = 1.6V and VOL = 1.4V. 8. At any given temperature and voltage condition for any given device, tLZCE is less than tHZCE and tLZOE is less than tHZOE. 9. tLZCE, tLZWE, tHZOE , tLZOE, t HZCE and t HZWE are tested with C L = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage. 10. This parameter is guaranteed but not tested. 11. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
5
CY7C133 CY7C143
Switching Characteristics Over the Operating Range[6] (continued)
7C133-25 7C143-25 Parameter tBLA tBHA tBLC tBHC tWDD tDDD tBDD tPS tWB tWH tWDD tDDD Description BUSY Low from Address Match BUSY High from Address Mismatch BUSY Low from CE LOW BUSY High from CE HIGH Write Pulse to Data Delay
[12]
7C133-35 7C143-35 Min. Max. 35 30 25 20 60 45 Note 13 5 0 25
7C133-55 7C143-55 Min. Max. 50 40 35 30 80 55 Note 13 5 0 30 Unit ns ns ns ns ns ns ns ns ns ns 80 55 ns ns
Min.
Max. 25 20 20 20 50 35 Note 13
BUSY/INTERRUPT TIMING (For Master CY7C133)
Write Data Valid to Read Data Valid[12] BUSY High to Valid Data[13] Arbitration Priority Set Up Time[14] Write to BUSY[15] Write Hold After BUSY
[16]
5 0 20 50 35
BUSY TIMING (For Slave CY7C143)
Write Pulse to Data Delay[17] Write Data Valid to Read Data Valid[17]
60 45
Switching Waveforms
Read Cycle No.1 [18, 19] Either Port Address Access
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C133-5
Notes: 12. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of "Read with BUSY, Master: CY7C133." 13. t BDD is a calculated parameter and is greater of 0,tWDD -tWP (actual) or t DDD-tDW (actual). 14. To ensure that the earlier of the two ports wins. 15. To ensure that write cycle is inhibited during contention. 16. To ensure that a write cycle is completed after contention. 17. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of "Read with Port-to-port Delay." 18. R/W is HIGH for read cycle. 19. Device is continuously selected, CE = VIL and OE = VIL .
6
CY7C133 CY7C143
Switching Waveforms (continued)
Read Cycle No. 2 [18, 20] Either Port CE/OE Access
CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
C133-6
Read Cycle No. 3 [19] Read with BUSY (For Master CY7C133)
tRC ADDRESS R R/WR DINR ADDRESS MATCH tPWE tHD VALID
ADDRESS L tPS BUSYL tBLA DOUTL
ADDRESS MATCH
tBHA tBDD VALID tDDD tWDD
C133-7
Note: 20. Address valid prior to or coincidence with CE transition LOW.
7
CY7C133 CY7C143
Switching Waveforms (continued)
Timing Waveform of Read with Port-to-port Delay No. 4 (For Slave CY7C143) [21, 22, 23]
tWC ADDRESSR MATCH tWP R/WR tDW DINR VALID tDH
ADDRESSL
MATCH tWDD
DOUTL tDDD
VALID
C133-8
Write Cycle No. 1 (OE Three-States Data I/Os - Either Port) [14, 24] Either Port
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN DATA VALID tHD tAW tPWE tHA
OE tHZOE HIGH IMPEDANCE DOUT
C133-9
Notes: 21. Assume BUSY input at VIH for the writing port and at VIL for the reading port.l 22. Write cycle parameters should be adhered to in order to ensure proper writing. 23. Device is continuously enabled for both ports. 24. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t PWE or t HZWE + t SD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required t SD.
8
CY7C133 CY7C143
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os--Either Port) [20, 25] Either Port
tWC ADDRESS tSCE CE tSA R/W tSD DATA IN tHZWE DATA OUT tHD tAW tPWE tHA
DATA VALID tLZWE HIGH IMPEDANCE
C133-10
Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First:
ADDRESS
L,R
ADDRESS MATCH
CEL tPS CER tBLC BUSYR tBHC
CER Valid First:
ADDRESS L,R CER tPS CEL
ADDRESS MATCH
tBLC BUSYL
tBHC
C133-11
Note: 25. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
9
CY7C133 CY7C143
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First:
tRC or tWC ADDRESS MATCH ADDRESS L tPS ADDRESS MISMATCH
ADDRESSR tBLA BUSYR tBHA
Right Address Valid First:
tRC or tWC ADDRESS MATCH ADDRESSR tPS ADDRESS MISMATCH
ADDRESS L tBLA BUSY L
C133-12
tBHA
Busy Timing Diagram No. 3 Write with BUSY (For Slave CY7C143)
CE
tPWE R/W
tWB BUSY
tWH
C133-13
10
CY7C133 CY7C143
Architecture
The CY7C133 (master) and CY7C143 (slave) consist of an array of 2K words of 16 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. The CY7C133 and CY7C143 have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. input of the slave. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. Flow-Through Operation The CY7C133/143 has a flow-through architecture that facilitates repeating (actually extending) an operation when a BUSY is received by a losing port. The BUSY signal should be interpreted as a NOT READY. If a BUSY to a port is active, the port should wait for BUSY to go inactive, and then extend the operation it was performing for another cycle. The timing diagram titled, "Timing waveform with port to port delay" illustrates the case where the right port is writing to an address and the left port reads the same address. The data that the right port has just written flows through to the left, and is valid either tDDD after the falling edge of the write strobe of the left port, or tDDD after the data being written becomes stable. Data Retention Mode The CY7C133/143 is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between VCC - 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 volts). Timing
Data Retention Mode VCC 4.5V VCC > 2.0V 4.5V tRC
V IH
Functional Description
Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Two R/W pins (R/WUB and R/WLB) are used to separate the upper and lower bytes of IO. Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flow-through delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. Busy The CY7C133 (master) provides on-chip arbitration to resolve simultaneous memory location access (contention). Table 2 shows a summery of conditions where BUSY is asserted. If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but which one is not predictable. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. The results of all eight arbitration possibilities are summarized in Table 3. BUSY is an open drain output and requires a pull-up resistor. One master and as many slaves as necessary may be connected in parallel to expand the data bus width in 16 bit increments. The BUSY output of the master is connected to the BUSY
CE
VCC to VCC - 0.2V
7C133-13
Parameter ICC DR1
Test Conditions @ VCCDR = 2V
[26]
Max. 1.5
Unit mA
Note: 26. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
11
CY7C133 CY7C143
Table 1. Non-Contending Read/Write Control Control R/WLB X L L H L H H H R/WUB X L H L H L H H CE H L L L L L L L OE X X L L H H L H I/O0-I/O8 High Z Data In Data In Data Out Data In High Z Data Out High Z I/O I/O9-I/O17 High Z Data In Data Out Data In High Z Data In Data Out High Z Operation Deselected: Power-Down Write to Both Bytes Write Lower Byte, Read Upper Byte Read Lower Byte, Write Upper Byte Write to Lower Byte Write to Upper Byte Read to Both Bytes High Impedance Outputs
Table 2. Address BUSY Arbitration Inputs CEL X H X L CER X X H L AddressL AddressR No Match Match Match Match BUSYL H H H Note 27 Outputs BUSYR H H H Note 27 Normal Normal Normal Write Inhibit[28] Function
Notes: 27. The loser of the port arbitration will receive BUSY = "L" (BUSYL or BUSYR = "L"). BUSYL and BUSYR cannot both be LOW simultaneously. 28. Writes are inhibited to the left port when BUSYL is LOW. Writes are inhibited to the right port when BUSYR is LOW.
32-Bit Master/Slave Dual-Port Memory Systems
R/W LEFT CY7C133 BUSY BUSY RIGHT R/W
5V R/W CY7C143 BUSY
5V R/W
BUSY
C133-14
12
CY7C133 CY7C143
Table 3. Arbitration Results Port Case 1 2 3 4 5 6 7 8 Left Read Read Read Read Write Write Write Write Right Read Read Write Write Read Read Write Write Winning Port L R L R L R L R
Result Both ports read Both ports read L port reads OK R port write inhibited R port writes OK L port data may be invalid L port writes OK R port data may be invalid R port reads OK L port write inhibited L port writes OK R port write inhibited R port writes OK L port write inhibited
Ordering Information
2K x16 Master Dual-Port SRAM Speed (ns) 25 35 55 Ordering Code CY7C133-25JC CY7C133-25JI CY7C133-35JC CY7C133-35JI CY7C133-55JC CY7C133-55JI Package Name J81 J81 J81 J81 J81 J81 Package Type 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial
2K x16 Slave Dual-Port SRAM Speed (ns) 25 35 55 Ordering Code CY7C143-25JC CY7C143-25JI CY7C143-35JC CY7C143-35JI CY7C143-55JC CY7C143-55JI Document #: 38-00414-B Package Name J81 J81 J81 J81 J81 J81 Package Type 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial
13
CY7C133 CY7C143
Package Diagram
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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